16ff+/28nm/40nm Expertise

Automated Design Flows with Customization for Complex Designs

Multi-Vt, Multi-mode, Multi-corner, Multi-supply

Low Power Design Methodologies

Flat and Hierarchical Design Methodologies

Clock & Power Gating

Minimal insertion and skews for clocks

High speed Clock Design & Synthesis

Advanced Clock Routing and Clock Spreading

Critical net routing & pre-routing with special requirements

On Chip Variation (OCV) & Advanced OCV

Signal Integrity Prevention, Fixing, Analysis

High Speed Interfaces – DDR3/DDR2/MDDR

Wire spreading, redundant via insertions

OD, Poly & Metal Dummy Fills

Power Planning & IR Drop Analysis

Design Implementation with Temperature Inversion Effects

Design For Manufacture (DFM) & Design for Yield (DFY) Techniques

OPC based routing

Compatibility with all leading foundry’s Reference Flows

First Time Silicon Successes!