Swati Design has around 60+ tapeouts during the last 17 years, with the following design statistics:

All Leading Processes (TSMC, Samsung, UMC, IBM, other foundries)
16ff+, 28nm, 40nm, 45nm, 65nm, 90nm, 130nm, 180nm, 250nm processes
All leading Libraries (Dolphin, Virage, TSMC, Artisan, True Circuits, Virtual Silicon, Nurologic, Aragio, Analog Bits, Synopsys, Custom)
Wide range of design implementations :
- Transistor Counts - 10 to 225+ million
- Die Sizes - 2mmX2mm to 21mmX21mm
- Core Utilizations - 98%+
- Clocks - 100MHz to 1.2+ Ghz
- Clock Domains - 6 to 80+
- I/O Pads - Inline, Staggered, Flip Chip from 400 to 3000
- Macros - Few to 400+ on a chip
- Macro Types - Multi-port RAM/ROMs, PLLs, DLLs, Serdes, etc.
- Design Types - Graphics, Networking, Communication, Processors, Video, Consumer, Cell Phones
- Design Styles - ASIC, Microprocessor, Data Path, Mixed Signal
Hierarchical Design Methodologies

Contact Information,
Email :info@SwatiDesign.com
Phone : (408) 828-0011

17 Years of Physical Design Services in Silicon Valley
60+ tapeouts with First Time Silicon Success!

Swati Design